Hardware Transactional Memory (HTM) is a mechanism in computer architecture for supporting parallel programming. With HTM, programmers may simply declare a group of instructions as being part of a single speculative region and the HTM hardware may then guarantee that the instructions in the region are executed as a single atomic and isolated transaction. Atomicity means that all the instructions of the transaction are executed as a single atomic block with respect to all other concurrent threads of execution on one or more other processing cores in the system. Isolation means that no intermediate result of the transaction is exposed to the rest of the system until the transaction completes. HTM systems may allow transactions to run in parallel as long as they do not conflict. Two transactions may conflict when they both access the same memory area (e.g., 8-byte word address) and either of the two transactions writes to that memory area (e.g., addressable 8-byte word).
To detect data conflicts between threads of execution, an HTM may keep track of which memory areas have been read from and/or written to speculatively during a transaction execution attempt. Memory areas that the processor tracks for the purposes of detecting data conflicts may be referred to as the read set (addresses the processor tracks as having been read) and the write set (addresses the processor tracks as having been modified) of the transaction. The read and write sets are often buffered in a speculative buffer, which is a logical entity that may be implemented by cache, load/store queue, both, and/or other hardware components.
Since HTM systems are implemented in hardware and therefore have limited resources with which to track read and write sets, various techniques have been used to make efficient use of HTM resources. One set of techniques is word grouping, whereby an HTM may group multiple addressable words and track them together in the read and/or write sets. For example, in response to detecting a speculative access to a given word in an active transaction, an HTM may mark the entire cache line in which the word resides (which holds multiple different addressable words) as being in the read or write set of the transaction. Marking a cache line may be done by setting a flag associated with the cache line. Thus, the HTM adds all the words in the cache line to the read or write set, even though only a single word in the group was speculatively accessed.
Another technique for making efficient use of HTM resources is early release. In this technique, the programmer is permitted to explicitly release an addressable word from the read set of an active transaction (e.g., using an explicit RELEASE instruction). For example, if a given transaction does not rely on a given read value beyond a certain point in the transaction, the programmer may explicitly remove from the read set, the memory address from which the value was read. Using such techniques, HTM designers have been able to increase the capacity of their systems and allow programmers to express and execute larger and more complex atomic memory transactions using HTM.